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Design Engineering
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181650 Requisition #
Join a verification team responsible for the verification of state of the art networking ASIC designs.
As part of the verification effort, new and advanced re-use methodologies are used. Full verification flow block-level to sub-chip and full-chip testbenches using SV-UVM, Specman & formal verification.
In this role, you’ll lead team of 5-10 verification engineers. Own full responsibility for the execution of the team, managing team’s personal development path and plenty of hands-on work.
  • Must have proven experience in leading complex technical tasks
  • Must have managerial experience
  • Must Have experience ASIC Verification using either SV-UVM and/or Specman
  • Must have good understanding of Verilog
  • Knowledge in Ethernet protocols - an advantage
  • Knowledge in PCIe - an advantage
  • Experience with Formal Verification - an advantage
  • Experience with scripting - an advantage
 
Personal skills:
 
  • Initiative
  • Ownership
  • Open minded
  • Strong execution orientation

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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