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Staff Verification Engineer - HBM/Memory Controller

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Design Engineering
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190520 Requisition #
Thanks for your interest in the Staff Verification Engineer - HBM/Memory Controller position. Unfortunately this position has been closed but you can search our 0 open jobs by clicking here.


Requirements:

  • Strong background in one of HBM, DDR4, DDR5 memory controller technologies, and relevant interface and protocol
  • Previous experience in System Verilog UVM based TB development, stimulus development including checkers and assertions

  • Working knowledge and experience on Verilog

  • Strong programming background on C++ and/or System Verilog
  • Knowledge of one of HBM, DDR4, DDR5 interface training, reliability is a plus
  • Knowledge of unix/linux environment, Makefiles and scripting (perl/python)

  • BS (EE or CS) required with 5-10 years relevant experience. MS (EE or CS) preferred
  • Self-motivated team player with excellent problem solving skills 

#LI-TM1

#GLDR


All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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