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Staff Physical Design Engineer

Physical Design & Layout
182694 Requisition #
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• Architect, implement, and maintain CAD flows that enable physical assembly of a high end server class processor chips in finfet process.
• Develop a stable CAD environment to enable unit owners to build, verify, and release blocks which are then used to assemble the chip.
• Define and develop assembly methodologies to create the full chip database, verify all signoff citeria were met, and then release to the foundry.
• Leading and mentoring junior employees and interfacing with front end design team to improve RTL and design quality.

• Experience performing place and route in finfet process
• Good understanding of concepts of timing and timing closure, cell-based place and route, clocking, fundamentals of logic design
• Expert in developing flows to drive block PnR, Timing Closure and Final sign off.
• Proficiency using Perl/Python, TCL, Make scripting.
• Prior experience with power/clk distribution and analysis, RC extraction and correlation, xtalk analysis, DRC/LVS and tapeout issues.
• Working knowledge of finfet issues.
• Experience with double pattern finfet  required, experience with triple pattern process nodes a plus.

Other Skills: 
• Demonstrates good analysis and problem-solving skills.
• Inherent sense of urgency and accountability.
• Ability to define problems, issues and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets.
• Ability to multi-task in a fast paced environment.

• MSEE 8+ years experience or BSEE with 10+ years related experience



All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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