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Design Engineering
182715 Requisition #
Thanks for your interest in the Staff Manager - DFT Design position. Unfortunately this position has been closed but you can search our 0 open jobs by clicking here.

Must have experience and knowledge of DFT concepts, including:

  • MemoryBIST (MBIST), Logic BIST (LBIST) and Memory Repair
  • JTAG Boundary Scan
  • iJTAG (1687)
  • Scan compression and ATPG generation, Test coverage analysis
  • SerDes BIST and IO BIST
  • Knowledge of Verilog, RTL coding, and multi-domain clock synchronization
  • Must have experience with On Chip clocking
  • Experience with Static Timing Analysis constraints at test mode
  • Experience with Design Tools, such as simulation, synthesis, waveform viewers, and debugging
  • Must have effective interpersonal, teamwork, and communication skills.
  • Must be able and willing to work independently.
  • Must have the ability to multi-task in a fast-paced environment
  • BS (EE or CS) with 7+ years or MS (EE or CS) required with 5+ years experience with DFT
  • 4+ years prior management or team lead experience. 

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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