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Staff Manager - DFT Design

Design Engineering
182715 Requisition #

In this role you will manage and lead a team responsible for design and development of large SOC chips with multiple processor cores.

  • Manage a team of DFT engineers who will be responsible for ATPG, Scan, MBIST, LBIST and silicon. 
  • Responsible for architecting the chip DFT strategy
  • Responsible for developing DFT flow methodology, implementation, and verification.
  • Responsible for pattern generation and validation.
  • Work with Logic, Verification and PD owners of design blocks to close on the DFT requirements.
  • Silicon Debug on ATE.
  • Resource and Schedule planning

Must have experience and knowledge of DFT concepts, including:

  • MemoryBIST (MBIST), Logic BIST (LBIST) and Memory Repair
  • JTAG Boundary Scan
  • iJTAG (1687)
  • Scan compression and ATPG generation, Test coverage analysis
  • SerDes BIST and IO BIST
  • Knowledge of Verilog, RTL coding, and multi-domain clock synchronization
  • Must have experience with On Chip clocking
  • Experience with Static Timing Analysis constraints at test mode
  • Experience with Design Tools, such as simulation, synthesis, waveform viewers, and debugging
  • Must have effective interpersonal, teamwork, and communication skills.
  • Must be able and willing to work independently.
  • Must have the ability to multi-task in a fast-paced environment
  • BS (EE or CS) with 7+ years or MS (EE or CS) required with 5+ years experience with DFT
  • 4+ years prior management or team lead experience. 

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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