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Staff Engineer - Physical Design

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Physical Design & Layout
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182417 Requisition #

We are seeking self-motivated engineers to be part of our central physical design team as we are expanding our team in India to grow our responsibility in implementing networking products. Being part of central engineering team candidate is expected to own and deliver block/chip level place and route assignments in cutting edge finfet technology process nodes.

Responsibilities: 
• Block/Chip physical design implementation and integration in finfet process

• Design Logic equivalence, timing/performance, xtalk checks

• Physical Verification for DRC/LVS, reliability and power checks

• Leading and mentoring junior employees and contractors in the team

• Interact with FE team to understand timing and CTS requirements and achieve best quality results

 

Requirements: 
• Hands on experience in PD flow from Netlist to GDSII in finfet process technologies 16nm or below

• Knowledge of MCMM optimization and multi power domain designs

• Strong knowledge in CTS implementation methodologies

• Experience in Physical Verification and closure in 16nm or below technology nodes.

• Experience in Static Timing Analysis with Signal Integrity.

• Experience in Synthesis, LEC, DFT is plus.

Other Skills

• Good communication and ability to work in team environment.

• Good problem solving skills

Tools:

• Innovus/ICC2, Calibre, Primetime-SI, Tempus, QRC/StarRC, LEC, Voltus

Education: 
• Masters in Engineering with 5+ years or Bachelors in Engineering with 8+ years of relevant experience

 

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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