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Staff Emulation Infrastructure Engineer

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Design Engineering
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182805 Requisition #
Successful candidate will be a hardware engineer, directly responsible for developing/maintaining/supporting hardware emulation infrastructure/flow of a complex ARM server CPU/SOC
  • Infrastructure development and bringup of a multi-core CPU/SOC in hardware emulation (Cadence palladium)
  • Develop/enhance/maintain methodology/tool flow for running assembly tests/SW applications/boot OS on hw emulator
  • Bringup new FPGA based methodology/HW platform and establish flow
  • Setup regression flow on the same for testing out different areas of the chip 
  • Use hw emulator effectively to test out various areas of the chip along with hw/sw co-simulation
  • Help reproduce post-silicon failures on hw emulator and help with reproduction of failures in hw emulator on simulation.
  • Closely work with RTL/verification engineers for debug and root-cause

  • Prior experience with hardware emulation (Synopsys Zebu, Cadence Palladium, Mentor Veloce, Synopsys HAPS, other FPGA/ASIC-based emulator) of a high-performance processor or SOC
  • Strong background in system integration and trouble-shooting
  • Strong programming (C/C++) and scripting skills (Perl, Python, etc)
  • Prior experience with methodology development for hardware emulation
  • Past experience with FPGA-prototyping bringup
  • Good working knowledge of Verilog, System Verilog and assembly programming
  • Must have effective inter-personal and teamwork skills
  • BS (EE or CS) required with 8+ years relevant experience. MS (EE or CS) preferred

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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