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Staff Design Engineer - Electrical Characterization

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Hardware Engineering
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181941 Requisition #
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As a characterization engineer you will join a small, focused team tasked with the electrical characterization and debug of both high speed SerDes (up to 32Gbps) and DDR4 ASIC interfaces.  Our team is involved with post silicon bring-up and debug as well as performing electrical characterization of high speed IO to support device production release.  

 

Responsibilities for the position include performing electrical characterization of analog circuits over process, voltage and temperature (PVT) variation to determine the viability of the silicon for production volume. The position requires the ability to design appropriate experiments and to automate these experiments in a lab environment.  This position allows for opportunities to learn detailed knowledge of the operation of state of the art analog circuits including; adaptive equalizers, clock & data recovery, analog and digital filter optimization, and interface/integration with analog functions.

 

In addition to the electrical characterization work you would be expected to lead a debug effort of either a DDR4 or SerDes interface.  We are looking for an individual who has extensive experience in at least one of these interfaces.  Experience with the analysis and debug of initialization and training sequences used by DDR4 (read/write leveling, VREF training, etc) is desirable.  For SerDes, experience with protocol-based link training sequences for PCIe Gen 3/4 and/or 10/25GBase-KR is preferred.

 

Our team believes strongly in continuous learning.  Third party training in automation, signal integrity analysis and PCB design is available to enhance your skills.  As part of a small team in a growing semiconductor company, there are many opportunities for advancement at Marvell.


#LI-KB1

#GLDR

Required skills for the position

* MSEE with 5+ years of experience or BSEE with 7+ years of experience with SerDes or DDR electrical characterization.

* Knowledge of Transmission line theory and s-parameter

* Knowledge of typical serial communication link impairments such as jitter, insertion loss, return loss and the ability to minimize the impact of these impairments with link equalization.

* Hands-on experience with test equipment, such as network analyzers/VNA, Bertscopes and Realtime Oscilloscopes

* Experience designing High Speed Printed Circuit Boards using Cadence Concept/Allegro

* Programming experience in Labview, Matlab and Python

 

Desired skills for the position

* Experience with Signal Integrity and/or Power Integrity simulation

* Experience with high speed SerDes protocols; PCIe, USB, SATA, Ethernet

* Experience with Jedec based DDR implementations

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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