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Sr Staff CPU/Caches Verification Engineer

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Design Engineering
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190519 Requisition #
Thanks for your interest in the Sr Staff CPU/Caches Verification Engineer position. Unfortunately this position has been closed but you can search our 0 open jobs by clicking here.

Requirements:


  • Good CPU architecture/micro-architecture knowledge  (one of MIPS/PowerPC/ARM/x86/SPARC architectures, CPU pipeline, out-of-order, superscalar, caches)
  • Working knowledge and experience on Verilog
  • Strong programming background on C++ and/or System Verilog
  • Knowledge of unix/linux environment and scripting (perl/python)
  • Knowledge/experience in memory consistency/coherency is a plus
  • BS (EE or CS) required with 5-10 years relevant experience. MS (EE or CS) preferred
  • Self-motivated team player with excellent problem solving skills

#LI-TM1

#GLDR


All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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