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Sr Staff Verification Engineer

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Design Engineering
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182248 Requisition #
Thanks for your interest in the Sr Staff Verification Engineer position. Unfortunately this position has been closed but you can search our 0 open jobs by clicking here.

Required:

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.

• Excellent written and verbal communication skills

• Excellent analytical problem solving skills

• Ability to work collaboratively in a team environment

• Experience with Verilog and SystemVerilog

• Demonstrated skills in ASIC/FPGA design and  simulations

• Experience with scripting and workflow automation


Desired:

• Experience using UVM

• Experience with synthesis and timing closure

• Experience with ATPG and test pattern generation

• Experience with leading or managing a small team

 

 

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All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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