Principal Physical Design Engineer - Power Analysis

Requirements: 

• Prior experience with power analysis on chips in finfet process, preferably on high frequency, high power designs with multiple power domains

• Basic understanding of microarchitectural concepts, ability to read verilog and simulation 

• Familiar with power saving techniques used in the physical design flow

• Proficiency with Spice and/or any fast simulator and hands-on power verification using spice

• Working knowledge of P&R implementation in finfet processes

• Proficiency using Perl/Python, TCL, Make scripting, calibre coding.

Other Skills: 

• Demonstrates good analysis and problem-solving skills.

• Inherent sense of urgency and accountability.

• Ability to define problems, issues and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets.

• Ability to multi-task in a fast-paced environment.

Education: 

• MSEE 8+ years’ experience or BSEE with 10+ years related experience