Sr Physical Design Engineer
Responsibilities:
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As a Physical Design Engineer (PnR), you will be part of our Implementation team and responsible for running/supporting/maintaining the PnR Flow using industry standard EDA tools for designing the next generation Multi-Ghz high-performance processor SOC chips in leading-edge CMOS process technology.
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Work with design teams across various disciplines such as Digital/RTL/Analog in helping them take their blocks (custom, PnR) through the physical design flow and making sure all the blocks meet timing requirements.
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Implement/Support blocks with multi-voltage designs through all aspects of RTL to GDS Implementation (Place and Route, static timing, physical verification) using industry standard EDA tools.
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Work with physical verification team in integrating these blocks seamlessly into full chip partitions. Have a good understanding of global integration and full chip physical verification.
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Provide technical direction, coaching, and mentoring to employees on the team and others when necessary to achieve successful project outcomes.
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Writing scripts in TCL and Perl to achieve productivity enhancements through automation is required.
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