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Sr. level Digital IC Design Engineer - SSD, RTL, ASIC Flows - HOT!!!

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Design Engineering
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180555 Requisition #
Thanks for your interest in the Sr. level Digital IC Design Engineer - SSD, RTL, ASIC Flows - HOT!!! position. Unfortunately this position has been closed but you can search our 363 open jobs by clicking here.
 

Minimum Qualifications:

o   MSEE with 2+ years of experience in RTL, ASIC design flows, etc.

o   Verilog RTL Design experience

o   Synthesis tools experience

o   LINT, CDC tools experience


 

Preferred Qualifications:

o   LINT, CDC tools experience

o   Scripting/programming language like PERL/Python, TCL and C/C++

o   Familiarity of ASIC design flow

o   Good communication and interpersonal skills

o   Knowledge of NVMe protocol is a plus.

o   Knowledge of NAND interface protocol (ONFI, Toggle) is a plus

o   Knowledge of SSD controller architecture is a plus

o   Knowledge of LDPC code design or algorithm is a plus

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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