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Sr. Staff Digital IC Design Engineer

📁
Design Engineering
📅
181218 Requisition #

Marvell first revolutionized the digital storage industry by moving information at speeds never thought possible!

 

Today, that same breakthrough innovation remains at the heart of the company's storage, network infrastructure, and wireless connectivity solutions. With leading intellectual property and deep system-level knowledge, Marvell's semiconductor solutions continue to transform the Enterprise, Data Center, SMB, Cloud, Automotive, Industrial, and Consumer markets.

 

You will be solving new technical challenges alongside leading industry professionals in an open, creative environment with plenty of opportunities for personal / professional growth.

 

Join our ambitious team within a multi-nation, multi-cultural company.  Marvell develops leading-edge products within a unique high-tech environment that motivates & encourages continued learning and growth!

 

 

What You Will Be Doing

You will work on SOC chips to design, implement and verify ATPG (Stuck-AT/AT-Speed) SCAN, Boundary SCAN, MBIST, IO BIST and JTAG/IJTAG DFT features. You will also work in close collaboration with test engineering team to deliver ATE patterns and post silicon bring-up and debug.

Your Key Responsibilities Will Include

• Work on SOC chip Stuck-AT/AT-Speed SCAN design and JTAG/IJTAG DFT features.

• Work with SOC team to design, implement and verify MBIST solutions on high speed memories on our SOC chips.

• Work in close collaboration with test engineering team to deliver ATE patterns and post silicon bring-up and debug.

 

Education & Experience Necessary for Success

• BSEE / MSEE, 8+ years of DFT experience

• Experience in DFT architecture, Hierarchical Scan Design, Scan insertion, Scan compression, Stuck-At, At-Speed test and coverage analysis.

• Experience in Mentor's latest DFT tool flow preferred.

• Experience in high speed MBIST design, implementation, simulation and debug on RTL and gates netlist

• Familiar with DFT timing constraints to close DFT timing in test mode STA

• Experience with front-end design methodology including STA, Formal Verification, Synthesis, Linting, CDC

• Familiar with script languages: Python, Perl, and TCL

 

#LI-LH1

#GLDR

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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