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Senior Verification Engineer - UVM

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Design Engineering
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181186 Requisition #
Thanks for your interest in the Senior Verification Engineer - UVM position. Unfortunately this position has been closed but you can search our 0 open jobs by clicking here.
  • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience.

  • Strong background in SoC verification methodology and test bench development using HVL such as Verilog, System Verilog, UVM 
  • Strong verification skills, understanding of methodology (object oriented programming, white-box/black-box, directed/random testing, coverage, gate-level simulations). 
 
Preferred/Plus: 
  • C/C++ programming skills
  • Prior experience in functional verification of Ethernet network system is preferred.
  • Knowledge of unix/linux environment and scripting (shell/Perl/Python) is a plus. 
Other Skills: 
  • Must have effective interpersonal and teamwork skills. Excellent communication skills. 
  • Ability to interface internally and externally with all levels of the organization. 
  • Participate in problem solving and quality improvement activities. 
  • Demonstrates good analysis and problem-solving skills. Inherent sense of urgency and accountability. Demonstrate initiative and a bias for thoughtful action. 
  • Grounded, detail-oriented, always backs up ideas with facts. Must have the ability to define problems, issues and opportunities, analyze data, establish facts, and draw valid conclusions from various data-sets. 
  • Must have the ability to multi-task in a fast paced environment.  

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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