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Senior Post-Silicon Validation Engineer

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Design Engineering
📅
182677 Requisition #

The Infrastructure Processor group within Marvell develops cutting-edge SOCs and processors in advanced process nodes for the largest telecommunications companies in the world. We develop the Octeon, Octeon-Fusion, and Armada chips for growing markets in exciting product segments. We are looking for motivated candidates who seek opportunities for professional growth and the chance to work in a dynamic organization with a world-class team in our Boise Design Center.


The Post-Si Validation Engineer within the Boise Design Center is responsible for running electrical, compliance, and margin testing on a wide variety of applications.  This role is for an individual contributor who will join a diverse hardware and software group that owns development and execution of electrical, system, and margin tests for silicon validation and characterization of multi-core ARM processors with high-speed SERDES. The silicon products tested include ARM processors (currently up to 48 cores) and high-speed SERDES (up to 100 GByte) with various protocols including Ethernet, PCIe, USB, SATA, SD, Flash, etc..


 Responsibilities:

  • Electrical characterization of high speed IO to support device production release
  • Conduct Compliance Testing on I/O interfaces including USB, PCIe, GigE, 10G, SATA, DDR, SFP+, …
  • Conduct Electrical characterization and margin testing against specification and across PVT.
  • Characterize silicon SERDES TX jitter and RX jitter tolerance, mask compliance, and bit error rate in lab test beds.
  • Understand standards for these I/O interfaces and requirements for meeting these standards.
  • Help in the process of Phy tuning in conjunction with internal and 3rd party designers.
  • With some guidance from senior engineers: plan, execute and document system stress tests for Marvell silicon products.
  • Assist with the design, build and test System Stress configurations using evaluation boards, internal software and the developed scripts/tests
  • Utilize Linux and scripting skills along with drivers from the internal software team to develop test benches that target exercising internal co-processor blocks.
  • Troubleshoot failing configurations with diagnostics, software tools, hardware analyzers, oscilloscopes, meters, logic/protocol analyzers with support from hardware and software engineers
  • Plan, execute and document test configurations and results.

Required Skills

  • Minimum - BSEE, BSCS Degree. Preferred Masters
  • Experience with test equipment, logic/protocol analyzers, and oscilloscopes.
  • Understanding of CPU Architecture and Computer Systems Design
  • Self-driven individual who works with a minimum of supervision and is a good team player with ability to work in cross-functional team
  • Write automation scripts for simulations, measurements, and post processing.
  • Provide reference platform design characterization and test reports as part of documentation set for customer solutions.  
  • Working knowledge of high speed SERDES transmitter and receiver equalization techniques.
  • Crisp and concise communication skills (both verbal and written) are required
  • Quality-minded, results-oriented
  • Able to work across disciplines and manage time across several demands

 

Desired Skills

  • Experience with scripting languages like Python or Perl.
  • C/++ programming, Linux, device drivers, and/or embedded software.
  • Experience and knowledge of lab measurement methodologies and equipment, including test automation methodologies and revision control
  • Understanding of measurement and analysis techniques for cross talk, insertion and return loss, phase noise, and bit error rate.
  • Experience with high bandwidth oscilloscopes, vector network analyzers, microprobes, Bertscopes, and phase noise analyzers for clocks, SERDES signal integrity, and power integrity test and measurement.
  • Experience with compliance measurements for SATA, PCIe3, USB, GigE, and DDR4 buses.
  • Understanding of board level passive channel design solutions for 20GHz+ SERDES circuits.
  • Familiarity with power distribution network impedance simulation and measurement
  • Experience with Performance benchmarking, measurement and debug.
  • Experience of hands-on testing and validation of I/Os across PVT


#LI-TM1

#GLDR

 

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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