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Senior Physical Design Engineer

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Physical Design & Layout
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182332 Requisition #
As a Senior Physical Design Engineer you will be a member of the Implementation team designing the next generation high-performance processor chips in leading edge CMOS process technology, targeted at network and consumer applications. 
  • You will be required to maintain, enhance, and support Cavium’s Place and Route Flow incorporating industry standard EDA tools
  • You will perform synthesis, floorplanning, place and route, timing analysis, and closure on complex logic blocks.
  • You will develop and implement timing and logic ECO’s.
  • You will interface with the RTL design team to drive design modifications to resolve congestion and timing issues.
  • You will work with the global timing team in debugging/resolving any block level timing issues seen at full chip.
  • You will test and maintain chip end-to-end flows, with specific focus on place and route and timing.
  • You will interface with tool vendors to drive tool fixes and improvements in support of on-going and planned CAD activities.   You might also perform tool evaluations of new vendor tools and functions.
Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience. 

Prior experience with synthesis, floorplanning, place and route, timing analysis, and closure on complex logic blocks.
Prior scripting experience with Perl, Tcl a plus

#LI-TM1

#GLDR


All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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