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Senior Engineer, Physical Design

Physical Design & Layout
180864 Requisition #

  • Implementing from Synthesis to GDSII that includes synthesis/DFT implement and check/P&R/ timing signoff and physical signoff
  • Cooperate with Project Manager on power fixing based on power analysis result
  • Develop methodologies to make daily work more efficient
  • Cooperate with designers on RTL issues which relative to backend timing closure and congestion solve.
  • Debugging the flow and completion it.
  • Can lead a team to take the responsible in Projects.

  • BS/MS+ in EE/CS required
  • Have DRC/LVS/ERC/Antenna debugging skills
  • Knows Synopsys /Cadence place-and-route tool set and physical design project implementation.
  • Good programming skill.
  • Capable of writing Tcl or Perl.
  • Familiar with synthesis, static timing analysis is an advantage.
  • Familiar with RTL Design in Verilog is an advantage..
  • Self-motivated team worker, good verbal and written communication skills in English.
  • 3+ years relative work experiences are preferred.
  • proved capabilities on leadership are required.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status

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