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Senior Design Verification Engineer

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Design Engineering
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180686 Requisition #
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Description

·   Work closely with design team to review the design spec and define detailed testplan

·   Develop UVM testbench at block level and SOC level for complex ASIC System-On-Chips

·   Run RTL and gate-level functional verification, debug failures, analyze and improve functional and code coverage

·   Develop and improve the verification flow and methodology


Requirements

·   Bachelors or Masters in Electrical, Computer, or Computer Science

·   Graduation with high GPA is a plus

·   Knowledge of ASIC design and verification flow including RTL design, simulation, synthesis, test bench development, etc.

·   Knowledge of System Verilog

·   Knowledge of UNIX environment, Perl, Shell scripting

·   Knowledge of verification methodology such as UVM/OVM/VMM is a plus

·   Knowledge of standard industry interface such as DDR, PCIE, SATA, SAS, USB, etc. is a plus

·   Good written and oral communication skills in English

·   Start working date: as soon as possible


All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status


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