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Design Engineering
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181845 Requisition #
Thanks for your interest in the RTL Design Intern position. Unfortunately this position has been closed but you can search our 0 open jobs by clicking here.
Requirements: 
  • Must have basic knowledge of computer architecture and logic design.
  • Must have some experience with Verilog/VHDL.

Preferred/Plus: 

  • Experience using FPGA design tools.
  • Knowledge of Python and/or C++.

Other Skills: 

  • Must have effective interpersonal and teamwork skills
  • Excellent communication skills
  • Ability to interface internally and externally with other departments.
  • Has an inherent sense of urgency and accountability.
  • Grounded, detail-oriented.
  • Must have the ability to multi-task in a fast paced environment.
  • Demonstrates good analysis and problem-solving skills.

Education: 

  • Must be currently enrolled in a BSEE/MSEE program (or equivalent).
  • Available for Internship from May 2019 to August 2019.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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