Physical Design Manager
- Proven technical leadership or mangaement in physical implementation (RTL to tapeout quality gds) of >2.5GHz finfet chips
- Coordinate across project disciplines (RTL, post silicon debug, marketing) to define physical design goals and tradeoffs to deliver a competitive product which meets customer requirements including schedule, frequency power and cost.
- Create and track the detailed milestones and dependencies from product definition to production ramp.
- Provide technical expertise in multiple critical domains of implementation such as floorplanning, timing, P&R, clock distribution, or power
and then insure this knowledge base is successfully implemented into the design resulting in a beneficial impact on the product
- Working knowledge of state of the architecture of state of the art processors
- Experience in post silicon debug and characterization of high speed processors
- Solid understanding of concepts of timing and timing closure, cell-based place and route, clocking, fundamentals of logic design
- Prior experience with power/clk distribution and analysis, RC extraction and correlation, xtalk analysis, DRC/LVS and tapeout issues.
- Experience working with EDA vendors in pre sales tool evaluation and post installation debug of tool issues
- Demonstrated analysis and problem-solving skills.
- Inherent sense of urgency and accountability.
- Excellent people skills and proven leadership experience
- Ability to multi-task in a fast paced environment.
- Coordinate across project disciplines (RTL, post silicon debug, marketing) to define physical design goals and tradeoffs to deliver a competitive product which meets customer requirements including schedule, frequency power and cost.
- Create and track the detailed milestones and dependencies from product definition to production ramp.
- Provide technical expertise in multiple critical domains of implementation such as floorplanning, timing, P&R, clock distribution, or power
and then insure this knowledge base is successfully implemented into the design resulting in a beneficial impact on the product
- Working knowledge of state of the architecture of state of the art processors
- Experience in post silicon debug and characterization of high speed processors
- Solid understanding of concepts of timing and timing closure, cell-based place and route, clocking, fundamentals of logic design
- Prior experience with power/clk distribution and analysis, RC extraction and correlation, xtalk analysis, DRC/LVS and tapeout issues.
- Experience working with EDA vendors in pre sales tool evaluation and post installation debug of tool issues
- Demonstrated analysis and problem-solving skills.
- Inherent sense of urgency and accountability.
- Excellent people skills and proven leadership experience
- Ability to multi-task in a fast paced environment.
