This job posting isn't available in all website languages

Physical Design Engineer

Physical Design & Layout
181977 Requisition #
  • As a Physical Design Engineer (PnR), you will be part of our Implementation team and responsible for running/supporting/maintaining the PnR Flow using industry standard EDA tools for designing the next generation Multi-Ghz high-performance processor SOC chips in leading-edge CMOS process technology.
  • Work with design teams across various disciplines such as Digital/RTL/Analog in helping them take their blocks (custom, PnR) through the physical design flow and making sure all the blocks meet timing requirements.
  • Implement/Support blocks with multi-voltage designs through all aspects of RTL to GDS Implementation (Place and Route, static timing, physical verification) using industry standard EDA tools.
  • Work with physical verification team in integrating these blocks seamlessly into full chip partitions. Have a good understanding of global integration and full chip physical verification.
  • Provide technical direction, coaching, and mentoring to employees on the team and others when necessary to achieve successful project outcomes.
  • Writing scripts in TCL and Perl to achieve productivity enhancements through automation is required.
  • BSEE with 4-6 years or MS with 2-4 years of experience running an industry standard EDA tools.
  • Knowledge of scripting languages such as Perl/TCL is required.
  • Experience in tape-outs of high performance SOC is highly desired.
  •  Understanding of several timing-related concepts is required: setup, hold, clocking, timing corners, timing constraints, noise, and process variation.
  • Physical design knowledge, from netlist handoff to GDS tape out including floor planning, place and route, clock tree synthesis, timing closure and physical verification.
  • Diligent, detail-oriented, and handle assignments with minimal supervision.
  • Must possess good communication skills, self-driven individual and a good team player.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Previous Job Searches

Activity Feed

Job shares through Marvell Semiconductor
Someone applied to the Sales - Account Management position. 55 minutes ago
Someone applied to the Intern - Verification Engineer position. 58 minutes ago
Someone applied to the Intern - Physical Design Engineer position. About an hour ago
Someone applied to the Hardware Engineering Intern position. About an hour ago
Someone applied to the Entry Level: Product Engineer position. About an hour ago

Similar Listings

United States, California, San Jose

📁 Physical Design & Layout

Requisition #: 181975