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Physical Design & Layout
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190183 Requisition #
Job description
 
The main responsibility of this job is foundry process  review to drive company decision on technology strategy. It will conduct in depth technology study and benchmark to support management on strategic decision on new technologies. It will compare device, interconnect and analog/digital performance between difference foundries and technology nodes. A major function is to create technical report such as power-performance-area (PPA) analysis of different processes.
 
This position will also be responsible for bringing up design flow. Focus will be SPICE model support, analog and mixed signal design simulation. Design complexity increases exponentially in Finfet technology. Specifically, SPICE models requires more sophisticated modeling of layout dependent effects, parasitics components,  noise modeling and mismatch modeling while maintain high level of accuracy. It requires close collaboration with IC design teams for adoption and support of design flow. In addition, creation and support of physical verification automation for use by design groups. Support tape-out and design-related foundry interface activities, as well as CAD flows for IP design and SOC integration.
 
Educational and Experience Prerequisites:
MSEE or PhD student in Electrical Engineering
 
The candidate should have knowledge or experience in:
  • Electronic Design Principles
  • Device Physics and Semiconductor Processing
  • SPICE model and simulation
  • Analog Design knowledge is plus
  • Unix Shell scripting, Perl, TCL, or Python 
  • Full Custom Design Tools
  • Strong verbal and written English communication

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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