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Physical Design & Layout
182626 Requisition #
Thanks for your interest in the Entry Level Professional position. Unfortunately this position has been closed but you can search our 0 open jobs by clicking here.
  • BS/MS in EE/CS with 5+ years of hands-on experience in frontend design integration (synthesis/timing), backend place and route or layout integration. Familiar with physical design methodologies and deep sub-micron technology issues. Familiar with ASIC design flow, Verilog HDL, chip synthesis and timing closure.
  • Must be programming-minded, write makefile/Tcl/Perl to automate design process and improve efficiency.
  • Detail oriented, self-motivated team worker, good verbal and written communication skills.
  • Good understanding of Synopsys suite (DCG, IC Compiler, IC Compiler 2), or Cadence suite (Genus Physical Design, EDI, Innovus).
  • Knowledge on static timing analysis (PrimeTime, Talus), EM/IR-Drop/Xtalk analysis (Tempus, PT-SI, Apache, PrimeRail), RC Extraction (StarRC, QRC, Quatus), formal or physical verification (Formality, Conformal/conformalLP, Calibre, IC Validator) a plus.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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