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Engineer, Senior Physical Design

Physical Design & Layout
181477 Requisition #
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• Develop and implement the clock methodology for high end server class processor chips in finfet process
• Responsible for developing clock distribution network to achieve low power low skew clocking solution.
• Leading and mentoring junior employees and interfacing with front/back end design team to improve clock solution for different type of blocks
• Experience in designing low skew, low power clock distribution networks and clock circuits in finfet process
• Understand issues of RC delay, electro-migration and cross talk
• Proficiency with Spice and/or any fast simulator and hands-on clock verification using spice
• Solid understanding of concepts of timing and timing closure, cell-based place and route, clocking, fundamentals of logic design
• Prior experience with RC extraction and correlation, DRC/LVS and tapeout issues.
• Scripting skills in Perl/Python, TCL, Make
• Knowledge of PLL design is plus
• Experience with double pattern finfet required, experience with triple pattern process nodes a plus.
Other Skills:
• Demonstrates good analysis and problem-solving skills.
• Inherent sense of urgency and accountability.
• Ability to define problems, issues and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets.
• Ability to multi-task in a fast paced environment.
• MSEE 8+ years experience or BSEE with 10+ years related experience

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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