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Digital IC Design Engineer

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Design Engineering
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182364 Requisition #

Responsibility:

Will work on the design implementation of our SSD controller chips.

Perform synthesis and pre- and post-layout timing closure and cooperate with P&R team to do the timing sign-off.

Perform DFT scan insertion and simulation, deliver ATPG pattern and help do the analysis.

Implement the power flow with upf/cpf

Perform other front-end design flow such as lint, CDC and Formal check.


Requirement:

Major in EE, CS or related with Master Degree.

Familiar with Verilog and RTL design

Familiar with script languages(perl,tcl,sh etc.)

Understand the timing and constraints

Understand basic DFT knowledges

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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