Digital IC Design Engineer
Responsibility:
·Will work on the design implementation of our SSD controller chips.
·Perform synthesis and pre- and post-layout timing closure and cooperate with P&R team to do the timing sign-off.
·Perform DFT scan insertion and simulation, deliver ATPG pattern and help do the analysis.
·Implement the power flow with upf/cpf
·Perform other front-end design flow such as lint, CDC and Formal check.
Requirement:
o Major in EE, CS or related with Master Degree.
o Familiar with Verilog and RTL design
o Familiar with script languages(perl,tcl,sh etc.)
o Understand the timing and constraints
o Understand basic DFT knowledges
