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Digital Design Intern (Serdes)

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Design Engineering
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190454 Requisition #

Marvell is actively seeking for high quality digital designers for internship to assist Marvell's central engineering SerDes PHY IP team. SerDes is one of the most important IP for any circuit design company that is in the business of storage, networking and cloud. Marvell’s SerDes has been one of the world-class leading designs and provided huge advantages to Marvell’s success.

 

The team's responsibility is to design and develop state of the art SerDes PHY IP from RTL to GDS, for both customer as well as internal SoC's fundamental building block. Our SerDes PHY supports standardized SAS 25G, PCIe 32G, USB 10G and Ethernet 100G to the latest possible industrial specifications.

 

Your responsibility as an intern is to assist senior designs for improving RTL design, set verification test cases, conduct timing analysis and achieve lower power design… You will also be working with project leads, DSP team, firmware team and provide innovative solutions to solve the real-world engineering challenges.

Minimum Education Experience:

Required: Bachelor’s in electrical Engineer

Preferred: Master's or PhD in Electrical Engineer

 

Minimum Qualification:

- Strong oral and written communication skills, team first spirit

- Verilog ASIC design techniques

- Fundamental signal processing knowledge

- Static Timing Analysis: Synopsys Primetime, Design Compiler

- Multiple clock domain design concept

- Fundamental Design Verification

  Preferred Qualification:

- Strong signal processing knowledge

- Knowledge of SystemVerilog, UVM

- Knowledge of Analog/Mix Signal

- Knowledge of Microcontroller, Assembly and C coding

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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