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Design Engineering
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182571 Requisition #

Marvell is actively seeking for high quality digital designers to assist Marvell's central SerDes PHY IP team. The team's responsibility is to design and develop state of the art SerDes PHY IP from RTL to GDS, for both customer as well as internal SoC's fundamental building block. Our SerDes PHY supports standardized SATA, SAS, PCIe, USB and Ethernet to the latest possible industrial specifications, it is the core IP team and one of the most fundamental driving strength to Marvell's success. RTL design, verification test cases, timing analysis, microcontroller firmware controls, protocol handling, signal processing circuit implementation, low power designs, IP delivery and schedule control… etc are the glances of our daily tasks. Your main responsibility will be working with project lead to deliver high quality SerDes PHY IP, and deal with all the real world engineering challenges.

1.1         Minimum Education Experience:

Required: Bachelor’s in electrical Engineer

Preferred: Master's or PhD in Electrical Engineer

 

 1.2       Minimum Qualification:

- Strong oral and written communication skills

- Verilog ASIC design techniques

- Static Timing Analysis: Synopsys Primetime, Design Compiler

- Multiple clock domain design concept

- Fundamental Design Verification

 

 1.3       Preferred Qualification:

- Strong signal processing knowledge

- Knowledge of SystemVerilog, UVM basics

- Knowledge of Analog/Mix Signal basics

- Knowledge of Microcontroller and C coding

 

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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