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Design Engineering
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181902 Requisition #

Responsibilities:  

  • Implement modern DFT solutions for leading edge ICs on latest technology nodes.
  • Understand and then implement the Cavium DFT architecture
  • Work with RTL, custom digital/analog, verification, physical implementation, and timing teams during this DFT implementation.
  • Set-up, run, and debug block-level, SOC-level as well as full-chip ATPG runs
  • Drive successful bring-up of test patterns and features post tape-out

#LI-KB1

#GLDR

Required:

  • Good understanding of scan test, functional test, JTAG, and other test methodologies
  • Some background in IC RTL design and using Verilog/SystemVerilog
  • Some knowledge of Synthesis and static timing process
  • Excellent programming skills with scripting languages such as Perl/TCL/Python
  • Demonstrate outstanding problem solving and analytic skills.

 Preferred/Plus: 

  • Understanding of chip debug features and capabilities strongly desired

 Other Skills: 

  • Must have effective interpersonal and teamwork skills.
  • Proficiency in working with cross functional and cross site teams.
  • Excellent communication skills
  • Has an inherent sense of urgency and accountability.

 Education: 

  • BSEE with 2+ years of experience in DFT

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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