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Design Engineering
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182917 Requisition #
Thanks for your interest in the Design Verification Manager position. Unfortunately this position has been closed but you can search our 0 open jobs by clicking here.

Requirements:

• Verification management experience in the one or more areas below is preferable

o  ARM CPU core

o Cache coherency

o Global coherency

o Experience on one or more interfaces – PCIe/USB/SATA etc..

• Good understanding of System Verilog, SVA and UVM

• Knowledge of Standard verification processes and methodology

• Experience on: regression, simulation time improvements, automation and tools used for generic verification

 

Other Skills:

• Effective management, planning, interpersonal and teamwork skills

• Excellent communication skills

• Good analysis and problem-solving skills

• Inherent sense of urgency and accountability

• Ability to multi-task in a fast-paced environment

 

Education:

• BS or MS Electrical/Computer Engineering with 12+ years relevant experience. MS EE preferred.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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