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Design Verification Engineer

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Design Engineering
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182360 Requisition #
Thanks for your interest in the Design Verification Engineer position. Unfortunately this position has been closed but you can search our 0 open jobs by clicking here.

Requirement:

o    Major in EE, CS or related with Master Degree.

o    Familiar with Verilog and RTL design

o    Familiar with System-Verilog and UVM verification methodology

o    Familiar with script languages(perl,tcl,sh etc.) is a plus

o    Good problem solving and communication skills

o     Good written and spoken English. Be able to work together with global team.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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