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Design Verification Engineer

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Design Engineering
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182360 Requisition #

Responsibility: 

o    Work together with global design team to develop testplan and testcases for SSD controllers. 

o    Maintain and help improve UVM based verification environment. 

o    Develop checker/driver and test cases to verify SSD controller IPs and SOCs.


Requirement:

o    Major in EE, CS or related with Master Degree.

o    Familiar with Verilog and RTL design

o    Familiar with System-Verilog and UVM verification methodology

o    Familiar with script languages(perl,tcl,sh etc.) is a plus

o    Good problem solving and communication skills

o     Good written and spoken English. Be able to work together with global team.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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