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Design Verification Engineer

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Design Engineering
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181677 Requisition #
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Responsibility: 
o    Work together with algorithm team and design team to develop testplan and testcases for various blocks in our Read Channel products. 
o    Maintain and help improve UVM based verification environment. 

o    Develop checker/driver and test cases to verify read channel designs.

o    Research on some advanced verification technology such as assertion based formal verification.


Requirement:

o    Major in EE, CS or related.

o    Familiar with Verilog and RTL design

o    Familiar with System-Verilog and UVM verification methodology

o    Familiar with script languages(perl,tcl,sh etc.) is a plus

o    Familiar with digital signal processing knowledge is a plus

o    Good problem solving and communication skills

o    Good written and spoken English. Be able to work together with global team.


All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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