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Engineering - Hardware
171013 Requisition #
Thanks for your interest in the Staff Verification Engineer position. Unfortunately this position has been closed but you can search our 0 open jobs by clicking here.
- Minimum of 5 years of work experience in Transceiver verification.
- Strong hands on experience in System Verilog and UVM.
- Familiar with constraint random based verification, functional coverage, code coverage and assertions.
- Experience in building BFM and C++ models of various SoC blocks.
- Experience in developing automation flow and scripts with Perl, Makefile, Tcl and UNIX shell.
- Knowledge of 802.3 IEEE standards, PTP IEEE 1588 and MACSEC is a plus.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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