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Design Engineering
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190439 Requisition #
Thanks for your interest in the Design Verfication Intern position. Unfortunately this position has been closed but you can search our 0 open jobs by clicking here.

Minimum Qualifications:

o   Candidate MUST be currently pursuing a BS/MS (preferred) degree in CS/EE or related technical field(s)

o   Basic understanding of Verilog and SystemVerilog

o   0-1 years of previous experience

 

Preferred Qualifications:

o   Excellent Design and Development experience, pursuing an MS in EE/CS and good verbal and written communication skills

o   Solid understanding of verification methodologies such as UVM/OVM/VMM

o   Strong Programming Skills in SystemVerilog/C++, in a Unix type environment, with good problem solving skills

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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