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Design Engineering
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181504 Requisition #

 

  • RTL design engineer responsible for all aspects of design including microarchitecture, RTL coding, simulation and debug
  • Work with architecture, verification, and implementation teams to complete a design that meet specifications and requirements

 

  • Must have experience with RTL languages such as Verilog or VHDL
  • Must have experience with the synthesis and static timing analysis
  • Experience with industry standard tools for all of these design steps, including simulation and synthesis, and timing analysis

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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