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Sr. Staff IC Design Engineer - ARM, Physical Design

Design Engineering
181282 Requisition #
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• Expert knowledge and experience performing place and route in finfet process

• Expert understanding of concepts of timing and timing closure, cell-based place and route, clocking, fundamentals of logic design

• Expert in developing flows to drive block PnR, Timing Closure and Final sign off.

• Proficiency using Perl/Python, TCL, Make scripting.

• Prior experience with power/clk distribution and analysis, RC extraction and correlation, xtalk analysis, DRC/LVS and tapeout issues.

• Proficiency with double pattern finfet  required, experience with triple pattern process nodes a plus.

Other Skills: 

• Demonstrates good analysis and problem-solving skills.

• Inherent sense of urgency and accountability.

• Ability to define problems, issues and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets.

• Ability to multi-task in a fast paced environment.


• MSEE 8+ years experience or BSEE with 10+ years related experience

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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