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Design Engineering - Design Verification

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Design Engineering
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182964 Requisition #
As a Senior Engineer, candidate will be responsible for developing verification plans and architecting test benches to validate DUT (Devise Under Test) functionality in simulation of application specific integrated circuit (ASIC/Integrated Circuit).
  • Interpreting architectural and design requirements;
  • Writing verification test plans and requirements;
  • Developing and using complex test benches;
  • Implementing directed and constrained random test cases;
  • Collecting, analyzing, and enhancing functional and code coverage;
  • Debugging issues in the requirements, tools, simulation environment, test cases, and DUT;
  • Performing Object Oriented programming (System Verilog);
  • Participating in System Verilog Verification using a framework such as UVM or other industry standard methodologies; 
  • Verification automation and scripting.
  • Hardware/Firmware interaction and Firmware programming; and, knowledge of Microprocessors and assembly language

BS or MS (Electrical or Computer Engineering ) or Equivalent Degree with 3+ years of experience

Proficient with SystemVerilog, HDL languages and Object Oriented Programming.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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