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Design Engineering - Design Verification

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Design Engineering
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180879 Requisition #

Work together with the global team on the design and verification of high-speed and low power digital circuits for the storage products.

  • Maintain and help improve our UVM based verification environment.
  • Build verification package for modules and new functions, write testplan and add testcases to keep improving the verification coverage.
  • Research on some advanced verification technology such as assertion based formal verification.


Requirement: 

o    Major in EE, CS or related, Master Degree with 2+ years or Bachelor with 5+ years working experiences in ASIC design or verification. 

o    Familiar with Verilog and RTL design 
o    Familiar with System-Verilog and UVM verification methodology
o    Familiar with script languages(perl,tcl,sh etc.) is a plus 
o    Familiar with digital signal processing knowledge is a plus 
o    Good problem solving and communication skills 
o    Good written and spoken English. Be able to work together with global team. 



All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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