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Design Engineering
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181652 Requisition #
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The engineer will take ownership over a unit or several units. He will do unit level design and verification and will plan and execute the verification. He will also participate in the cluster level verification.
The engineer will work with architects to understand and influence the unit architecture, plan and implement design changes in Verilog or SV, plan and implement verification environment in UVM, and execute the verification plan until quality criteria is met.
  • Electrical engineering B.Sc graduate
  • Design RTL experience in Verilog or SV
  • Verification experience in SV, UVM, perl,
  • Knowledge in programming
  • Good learning skills
  • Problems solving skill
  • Ability to be a part of a team, working in cooperation

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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