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Design and Verification engineer

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Design Engineering
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181654 Requisition #
The engineer will join the cluster verification team taking ownership over cluster related tasks such as: Generation/Test-Bench/Reference Model. He will also take part in specific features verification (FWS & performance testing, PFC, etc)
The engineer will participate in the verification plan activities and will influence u-Arch, design and verification tasks. He will also need to work with Chip-Design verification team, supporting them with integrating our environment in Full-Chip verification environment
    • Electrical engineering B.Sc graduate
    • Design RTL experience in Verilog or SV
    • Verification experience in SV, UVM, perl,
    • Knowledge in programming
    • Good learning skills
    • Problems solving skill
    • Ability to be a part of a team, working in cooperation

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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