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Associate Verification Design engineer

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Design Engineering
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181051 Requisition #
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We are offering you a great opportunity to join  the Switch IP department and be part of the IP development for the next generation Switch.

As a student in the IP department you’ll be responsible for design and verification of ASIC/VLSI of a complex IP.

You will be working with Verilog, System Verilog, UVM, C++, Perl, Python, System C

You will become a design and verification engineer.


·         Student for Electrical engineering B.Sc

·         Knowledge of logical gates

·         Knowledge in programming

·         Good learning skills

·         Problems solving skill

·         Ability to be a part of a team, working in cooperation


All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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