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Analog IP Integration Layout Designer

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Physical Design & Layout
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182650 Requisition #

Marvell is looking for an experienced layout designer to work with the Analog Design Team and Physical Integration teams to integrate multiple analog IP blocks into large SOCs. IP include: PLLs, SERDES, DDR, ADCs, GPIO, etc.

 

Responsibilities Include:

  • Floorplanning blocks and partitions
  • Custom layout for critical signal routing, hook up structures, and custom analog circuits
  • Running all necessary physical design verification and addition tool steps to clean blocks in the ASIC flow
  1. Custom Analog Layout experience, preference on large scale ASICs
  2. Tools: Cadence Virtuoso, Common DRC/LVS toolset
  3. Languages: Perl, TCL, SKIL a plus
  4. Ability to communicate well in writing and coordinate multi-site work
  5. Experience: 5-10 yrs

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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